Revision as of 11:28, 17 November 2011

The Western Digital TV Live is a media player running a Sigma Designs SMP8655 (Non Macrovision version of the SMP8654).

It sports three processors combined into the SoC, a 500MHz MIPS 24KF main CPU+FPU, a 333MHz MIPS 4KEc IPU (Image Processing Unit) and a 333MHz Security CPU supporting conditional access (CA) and digital rights management (DRM).

~ # cat /proc/cpuinfo
system type  : Sigma Designs TangoX
processor  : 0
cpu model  : MIPS 24K V7.12 FPU V0.0
Initial BogoMIPS  : 332.59
wait instruction  : yes
microsecond timers  : yes
tlb_entries  : 32
extra interrupt vector  : yes
hardware watchpoint  : yes
ASEs implemented  : mips16
shadow register sets  : 1
VCED exceptions  : not available
VCEI exceptions  : not available

System bus frequency  : 333000000 Hz
CPU frequency  : 499500000 Hz
DSP frequency  : 333000000 Hz


FLASH Memory

The board contains a single Micron MT29F2G08AAD NAND FLASH with a capacity of 2Gbits x 8 (256MBytes).

/proc # cat sigminfo dev: size offset name CS sigmblk0: 0ff80000 00000000 "CS0-Device" 0
sigmblk1: 00080000 00000000 "CS0-Part1" 0
sigmblk2: 00040000 00080000 "CS0-Part2" 0
sigmblk3: 00300000 000c0000 "CS0-Part3" 0
sigmblk4: 00300000 003c0000 "CS0-Part4" 0
sigmblk5: 01000000 006c0000 "CS0-Part5" 0
sigmblk6: 00800000 016c0000 "CS0-Part6" 0
sigmblk7: 05a00000 01ec0000 "CS0-Part7" 0
sigmblk8: 05a00000 078c0000 "CS0-Part8" 0
sigmblk9: 00020000 0d2c0000 "CS0-Part9" 0
sigmblk10: 00020000 0d2e0000 "CS0-Part10" 0
sigmblk11: 00020000 0d300000 "CS0-Part11" 0


/dev # ls -l /dev/mtd* brw-r--r-- 1 root root 254, 0 Jan 1 2000 /dev/mtdblock0 brw-r--r-- 1 root root 254, 3 Jan 1 2000 /dev/mtdblock2 brw-r--r-- 1 root root 254, 6 Jan 1 2000 /dev/mtdblock3 lrwxrwxrwx 1 root root 15 Jan 1 2000 /dev/mtdblock_bootloader -> /dev/sigmblocka lrwxrwxrwx 1 root root 15 Jan 1 2000 /dev/mtdblock_kernel -> /dev/sigmblockd lrwxrwxrwx 1 root root 15 Jan 1 2000 /dev/mtdblock_romfs -> /dev/sigmblockh

ls -l /dev/sigmblock* brw-rw---- 1 root root 254, 0 Jan 1 2000 /dev/sigmblocka brw-rw---- 1 root root 254, 1 Jan 1 2000 /dev/sigmblockb brw-rw---- 1 root root 254, 2 Jan 1 2000 /dev/sigmblockc brw-rw---- 1 root root 254, 3 Jan 1 2000 /dev/sigmblockd brw-rw---- 1 root root 254, 4 Jan 1 2000 /dev/sigmblocke brw-rw---- 1 root root 254, 5 Jan 1 2000 /dev/sigmblockf brw-rw---- 1 root root 254, 6 Jan 1 2000 /dev/sigmblockg brw-rw---- 1 root root 254, 7 Jan 1 2000 /dev/sigmblockh brw-rw---- 1 root root 254, 8 Jan 1 2000 /dev/sigmblocki brw-rw---- 1 root root 254, 9 Jan 1 2000 /dev/sigmblockj brw-rw---- 1 root root 254, 10 Nov 12 12:51 /dev/sigmblockk brw-rw---- 1 root root 254, 11 Jan 1 2000 /dev/sigmblockl

sigmblocka signblockc YAMON sigmblockd vmlinux_xload.zbf sigmblocke vmlinux_xload.zbf sigmblockh

sigmblockf Splash Screens

RAM Memory

Four 1Gbit Nanya NT5TU64M16DG-AC DDR2-800 SDRAMs have been used for volatile memory providing a total 512Mbytes of RAM.

YAMON PROM Monitor

The board uses MIPS's YAMON PROM Monitor as the bootloader. Source code is available from here.

To break into the YAMON console while booting, press the 0 key.

To initialise the network and obtain an IP address via DHCP:

YAMON> net init
em86xx_eth0 ethernet stop

em86xx_eth0 - full-duplex mode
em86xx_eth0 - 100 Mbit/s
em86xx_eth0 ethernet start
DHCP was successfully configured.
ipaddr: 192.168.0.50
subnetmask: 255.255.255.0
gateway: 192.168.0.254


To load a kernel into memory from TFTP:

YAMON> load -b tftp://192.168.0.251/vmlinux.bin 0x84000000

And then execute:

YAMON> go

Kernel

The YAMON bootloader requires a binary version of the kernel. Use objcopy to generate this file from the vmlinux ELF file.

mipsel-linux-objcopy -O binary vmlinux vmlinux.bin