View source for OV7670 Camera Module with AL422 FIFO Theory of Operation


== OV7670 Camera Module with AL422 FIFO - Theory of Operation ==

These notes are for the OV7670 AL422 FIFO Camera Module avaliable from a range of suppliers on the internet including [http://www.emartee.com/product/42043/OV7670%20AL422%20FIFO%20Camera%20Module%20CF7670C%20V2 Emartee].

The image sensor can be controlled using the Serial Camera Control Bus (SCCB). This is an I2C interface with a maximum clock frequency of 400KHz.

The sensor can output the following formats on the 8 bit interface:
* YUV/YCbCr 4:2:2
* RGB565/555/444
* GRB 4:2:2
* Raw RGB 

In addition to the 8 data lines, the following handshaking signals exist:
* VSYNC – Vertical sync output – Low during frame
* HREF – Horizontal reference – High during active pixels of row
* PCLK – Pixel clock output – Free running clock. Data is valid on rising edge.

The OV7670 is clocked from a 24MHz oscillator. This provides a pixel clock (PCLK) output of 24MHz.

The Averlogic AL422B provides 3Mbits of video frame buffer memory configured as a 393,216 byte x 8 bit FIFO.

The internal memory of the AL422B is DRAM and requires continuous refreshing. The fastest clock applied to either the write clock (WCK) or the read clock (RCK) is used as the DRAM refresh timing clock. The datasheet recommends that the WCK and RCK are kept free running at least 1MHz at all times.

While the OV7670’s pixel clock (PCLK) can be turned off during horizontal blanking COM10 bit 5, the PCLK is feed directly into the write clock (WCK) pin of the AL422B for DRAM refreshing. To prevent clocking the horizontal blanking data into the FIFO, a NAND gate (U1) is used to invert the HREF output and feed this signal into the write enable (WE) pin of the AL422. The second input of the NAND gate is provided as a user controllable active high write enable (WEN).

== Version 1.0 / Version 2.0 ==

It appears two versions of the OV7970 Camera Module with AL422 FIFO exist. 
Apart from the addition of resistors on the SCCB, pin 6 on the version 1 module is designated as write reset (WRST) and pin 6 on the version 2 module is designated as HREF. 

On the version 2 module, VSYNC from the OV7670 image sensor is connected directly to the AL422’s write reset (WRST). The concept is a low on the VSYNC (start of frame) can reset the write counter of the FIFO automatically. For this to occur, the VSYNC signal needs to be inverted. This can be done by setting COM10, bit 1 (VSYNC negative).

== Schematics ==

* [http://www.beyondlogic.org/pdf/OV7670_FIFO_SCH_V1.pdf Version 1 Schematics]
* [http://www.beyondlogic.org/pdf/OV7670_FIFO_SCH_V2.pdf Version 2 Schematics]